1. Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes related to the planarization of wafer surfaces by the application of spin-on glass layers.
2. Background to the Invention and Description of Previous Art
Integrated circuits(ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices, contacting their active elements and wiring them together to create the desired circuits. The wiring layers are formed by depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into these openings. A conductive layer is then applied over the insulating layer and is patterned to form wiring interconnections between the devices, thereby creating a level of basic circuitry. The basic circuits are then further interconnected by utilizing additional wiring levels laid out over additional insulating layers with via pass throughs.
Spin-on coatings have been used in integrated circuit manufacture for many years. These are materials can be applied in liquid form and subsequently hardened or cured to form solid or semi solid layers. The most familiar spin-on materials are photoresists and polyimides which have been used since the early 1970s. The photoresists, of course, are generally used for patterning only and as such, are transient films and do not remain in the finished product. Polyimide films have been used from time to time as dielectric and filler layers but frequently suffer processing incompatibilities such as severe outgassing, thermal instability and deformation by shrinkage. More recently, spin-on glasses(SOGs) have received widespread use and success in wafer surface planarization but have also been plagued by outgassing causing blistering and corrosion problems.
Each time a layer of metallization is formed on an integrated circuit wafer and circuit paths are etched within it, the metal pattern introduces a non-planar surface. When the next insulative layer is deposited, by conformal methods such as CVD (chemical vapor deposition), the irregular surface topology is replicated at the insulative layer surface. In order to prevent the cumulative replication of subjacent metal pattern topologies throughout the various metallization levels, it has become common practice in multi-level integrated circuit manufacture to include a means for planarizing each insulative layer prior to deposition of a metallization layer.
One method for achieving a such planarization method involves the deposition of an SOG in a liquid form, for example a liquid monomer which, when spun onto the wafer surface, flows into the topological contours. After deposition, the material is dried and cured to form a polymeric insulative film with a smooth, essentially planar, surface for deposition of a subsequent metal layer. The SOGs consist of alcohol soluble silicates and siloxanes which can attain the properties of inorganic glasses when properly cured. The SOGs have found wide acceptance in recent sub-micron semiconductor processing technology because of their low defect density, simplified processing, and low thermal budget. However, the SOG layers have been generally limited to thicknesses of only a few thousand Angstroms. Thicker layers tend to crack and require longer and more careful curing times. A common method of usage is to first deposit a layer of PECVD(plasma-enhanced CVD) silicon oxide over a layer of patterned metallization and then lay the SOG over it. The SOG fills in the narrow features. It is then etched back by anisotropic etching to the PECVD oxide surface. The result is the original PECVD layer with the small spacings filled with SOG.
The SOG is deposited by a nozzle directed at the center of a rapidly spinning wafer. Centrifugal force distributes the liquid over the wafer. Excess liquid is flung from the edge of the wafer. The apparatus used to perform this task is of the same type that is conventionally used to deposit photoresist. The wafer is then allowed to dry briefly and then the SOG is cured, typically by a sequence of hot plate baking steps. The curing process is difficult in that it requires a delicate balance between the rate of solvent and polymerization by-product removal and the rate of formation of the polymer. Failure to provide the proper balance results in cracking and inclusion of impurities which can produce cause subsequent metal corrosion. Residual solvent, moisture and polymerization by-products due to improper or insufficient curing can bring about bubble formation and blistering in films subsequently deposited on the SOG layer. Not only are SOG films subject to contain curing residuals, they are also prone to absorb moisture and contaminants from the atmosphere. It has been demonstrated by Wang, U.S. Pat. No. 5,554,567, that SOG films left in the open air after curing for more than about three hours were prone to blistering when an insulative layer was then deposited over them.
Much effort has been devoted to improve the gap-filling and planarization aspects of spin-on glasses while at the same time making the films more stable and free of agents which cause out-gassing and decomposition of the SOG as well as corrosion and degradation of adjacent integrated circuit elements. Yen, et.al., U.S. Pat. No. 5,716,673 cite a process for improving planarity and gap filling by SOGs by slowing the evaporation rate of solvent after deposition by slow-spinning the deposited SOG in a controlled environment.
Vidusek, U.S. Pat. No. 5,370,969 reports out-gas resistant planarization materials which can be spin deposited like an SOG. A novolac polymer, and polydimethyl-glutarimide are cited as non nitrogen bubble generating materials. These materials are used in a planarization process to facilitate a photo lithographic process and are thereby transitory and not becoming a permanent part of the integrated circuit. These materials are unstable at temperatures above 300.degree. C. and will decompose when during subsequent processing procedures which call for higher temperatures. Hung, et.al., U.S. Pat. No. 5,694,207 shows a method for monitoring the etch rate of an SOG layer by optical emission spectroscopy.
Methods for easy, reliable detection of residues, left behind in various processing steps, in particular, chemical stripping operations of photoresist, have been developed over the years. Many of these methods involve means for making the defective sites more visible. This procedure is commonly referred to as decoration. The procedure is accomplished by enlarging the defect site by selectively etching of material exposed by the defect. Chinn, et.al., U.S. Pat. No. 5,223,443 describes a method for decorating sites where particles of photoresist have been left behind on a polysilicon layer after an inadequate photoresist strip. A thin layer of silicon oxide is deposited on the wafer. The layer is so thin that the photoresist particles remain exposed. The residue sites are then decorated by an etch in aqueous KOH whereby, not only are the photoresist particles removed, but the subjacent polysilicon is attacked, making the site easily visible.
Micro bubbles tend to form in SOG layers and in layers of silicon oxide deposited over cured SOG layers. The micro bubbles result from out-gassing of the SOG layers during the silicon oxide deposition. Because the silicon oxide layers are relatively thin, the micro bubbles are prone to cause pinholes and virtual defects which are of reliability concern in the silicon oxide layers. In a process wherein the SOG layer and the silicon oxide top layer comprise an interlayer dielectric(ILD) or intermetal dielectric(IMD), the pinholes and defects caused by the SOG bubbles in silicon oxide layers deposited over SOG bring about abnormal vias, via-via shorts, metal opens, and metal bridging shorts. It is of great importance to have a timely method for detection and identification of micro bubble problems in dielectric layers involving SOG. Such a method is provided by this invention.